View MCM64AF32SG15_1277810.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM64AF32/D
Product Preview
MCM64AF32
160-LEAD CARD EDGE CASE TBD* TOP VIEW 1
256K Asynchronous Secondary Cache Module for PentiumTM
The MCM64AF32 is designed to provide 256K of asynchronous L2 cache for the Pentium microprocessor in conjunction with Intel's Triton chip set. The module is configured as 32K x 64 bits in a 160 pin card edge connector. The module uses eight Motorola 3.3 V 32K x 8 FSRAMs for the cache memory, one Motorola 5 V 32K x 8 FSRAM for the tag RAM, and an upper order address latch. Eight write enables are provided for byte write control. PD0-PD4 identify density and functionality. This cache module is plug and pin compatible with the other members of Motorola's Triton chip set module family, the MCM72JG32SG66 (a 256K byte pipelined BurstRAM module) and the MCM72JG64SG66 (a 512K byte pipelined BurstRAM module). * Low-Cost Asynchronous Solution for Triton Chip Set * All Cache Data Inputs and Outputs are LVTTL (3.3 V I/O) Compatible * All Tag I/Os are TTL Compatible * Byte Write Capability * Fast SRAM Access Times:15 ns for Data RAMs and Tag RAM * Decoupling Capacitors for each Fast Static RAM and Logic Device * High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes * 160 Pin Card Edge Module * Burndy Connector, Part Number: CELP2X80SC3Z48
42 43
80
* SEE BACK PAGE FOR PRELIMINARY * SEE CHAPTER 9 FOR PRELIMINARY CASE OUTLINE. CASE OUTLINE.
BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM64AF32 1
PIN ASSIGNMENT 160-LEAD CARD EDGE MODULE TOP VIEW
PRESENCE DETECT TABLE
Cache Size and Functionality 256KB Async 512KB Async 256K Burst 256K Pipe Burst 512K Burst 512K Pipe Burst 512K 2-Bank Burst
Module MCM64AF32 -- -- MCM72JG32 -- MCM72JG64 --
PD4 VSS VSS VSS VSS VSS VSS VSS
PD3 NC VSS NC NC VSS VSS VSS
PD2 VSS NC VSS VSS NC NC NC
PD1 VSS VSS NC NC NC NC VSS
PD0 NC NC VSS NC VSS NC VSS
VSS TIO1 TIO7 TIO5 TIO3 (RSVD) NC VCC5 (RSVD) NC (CADV) CAA4 VSS COE CWE5 CWE7 CWE1 VCC5 CWE3 CAB3 CALE VSS (RSVD) NC (A4) NC A6 A8 A10 VCC5 A17 VSS A9 A14 A15 (RSVD) NC PD0 PD2 PD4 VSS (CLK0) NC VSS DQ63 VCC5 DQ61 DQ59 DQ57 VSS DQ55 DQ53 DQ51 DQ49 VSS DQ47 DQ45 DQ43 VCC5 DQ41 DQ39 DQ37 VSS DQ35 DQ33 DQ31 VCC5 DQ29 DQ27 DQ25 VSS DQ23 DQ21 DQ19 VCC5 DQ17 DQ15 DQ13 VSS DQ11 DQ9 DQ7 VCC5 DQ5 DQ3 DQ1 VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VSS TIO0 TIO2 TIO6 TIO4 NC (RSVD) VCC3 TWE CAA3 (CADS) VSS CWE4 CWE6 CWE0 CWE2 VCC3 CAB4 (CCS) NC (GWE) NC (BWE) VSS NC (A3) A7 A5 A11 A16 VCC3 NC (A18) VSS A12 A13 NC (ADSP) NC (CS/ECS1) NC (ECS2) PD1 PD3 VSS NC (CLK1) VSS DQ62 VCC3 DQ60 DQ58 DQ56 VSS DQ54 DQ52 DQ50 DQ48 VSS DQ46 DQ44 DQ42 VCC3 DQ40 DQ38 DQ36 VSS DQ34 DQ32 DQ30 VCC3 DQ28 DQ26 DQ24 VSS DQ22 DQ20 DQ18 VCC3 DQ16 DQ14 DQ12 VSS DQ10 DQ8 DQ6 VCC3 DQ4 DQ2 DQ0 VSS
PIN NAMES
TIO0 - TIO7 . . . . . . . . . . . . . . . . . . . . . Tag RAM I/O TWE . . . . . . . . . . . . . . . . . . . . . . . . Tag Write Enable CALE . . . . . . . . . . . . . . . . . . . Address Latch Enable A5 - A17 . . . . . . . . . . . . . . . . . . . . . . Address Inputs CWE0 - CWE7 . . . . . . . . . . . Cache Write Enable CAA3 -CAA4 . . . . . . . . . . . . . . . . Cache Address A CAB3 - CAB4 . . . . . . . . . . . . . . . Cache Address B COE . . . . . . . . . . . . . . . . . . . . Cache Output Enable DQ0 - DQ63 . . . . . . . . . . . . . . . . Data Input/Output PD0 - PD4 . . . . . . . . . . . . . . . . . . Presence Detect VCC3 . . . . . . . . . . . . . . . . . . . + 3.3 V Power Supply VCC5 . . . . . . . . . . . . . . . . . . . + 5.0 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connection For proper operation of the device, VSS must be connected to ground.
NOTE: Signals in parentheses indicate pin designations for burstable members of the Triton chip set module family.
MCM64AF32 2
MOTOROLA FAST SRAM
MCM64AF32 MODULE BLOCK DIAGRAM
32K X 8 5V DQ0 - DQ7 A0 - A12 E W G A13 - A14 13 32K X 8 3.3 V A0 - A1 A2 - A14 W E G DQ0 - DQ7 32K X 8 3.3 V A0 - A1 A2 - A14 W E G DQ0 - DQ7 32K X 8 3.3 V A0 - A1 A2 - A14 W E G DQ0 - DQ7 32K X 8 3.3 V A0 - A1 A2 - A14 E W DQ0 - DQ7 G 32K X 8 3.3 V A0 - A1 A2 - A14 E W DQ0 - DQ7 G 32K X 8 3.3 V A0 - A1 A2 - A14 E W DQ0 - DQ7 G 32K X 8 3.3 V A0 - A1 A2 - A14 W E G DQ0 - DQ7 32K X 8 3.3 V A0 - A1 A2 - A14 E W DQ0 - DQ7 G
TIO0 - TIO7 CALE LE A5 - A17 CAA3 - CAA4 13 '373 2
TWE
COE A18 - NC
8
CWE0 DQ0 - DQ7
8
CWE1 DQ8 - DQ15
8
CWE2 DQ16 - DQ23
8
CWE3 DQ24 - DQ31
CAB3 - CAB4
2
8
CWE4 DQ32 - DQ39
8
CWE5 DQ40 - DQ47
8
PD0 - NC PD1 PD2 PD3 - NC PD4
CWE6 DQ48 - DQ55
8
CWE7 DQ56 - DQ63
MOTOROLA FAST SRAM
MCM64AF32 3
PIN DESCRIPTIONS
160-Lead Card Edge Pin Locations 21, 22, 23, 24, 28, 29, 102, 103, 104, 106, 108, 109, 110 9, 89 16, 97 98 11, 12, 13, 14, 92, 93, 94, 96 8 -- 91 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 2, 3, 4, 5, 82, 83, 84, 85 Symbol A5 - A17 Type Input Description Address Inputs: These inputs are latched into data RAMs and must meet setup and hold times. The tag RAM addresses are not latched. (See Block Diagram). Cache Address A: Low order address inputs for bursting. Not latched. Cache Address B: Low order address inputs for bursting. Not latched. Address Latch Enable: Active low signal latches A5 - A17. Cache Data Write Enable: Active low write signal for data RAMs. Tag Write Enable: Active low write signal for tag RAMs. Chip Select: Active low chip enable for tag and data RAMs. Not used. Cache Output Enable: Asynchronous active low output enable for data RAMs. Data I/O
CAA3, CAA4 CAB3, CAB4 CALE CWE0 - CWE7 TWE CS COE DQ0 - DQ63
Input Input Input Input Input Input Input I/O
TIO0 - TIO7 PD0 - PD4 VCC3 VCC5 VSS
I/O
Tag RAM I/O: Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles. Presence Detect: See Presence Detect Table.
33, 34, 112, 113, 114 7, 15, 25, 39, 52, 60, 68, 76 87, 95, 105, 119, 132, 140, 148, 156 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 6, 17, 18, 20, 26, 30, 31, 32, 36, 86, 88, 100, 101, 111, 116
Supply Supply Supply
Power Supply: 3.3 V 5%. Power Supply: 5.0 V 5%. Ground
NC
--
No Connection: There is no connection to the module.
MCM64AF32 4
MOTOROLA FAST SRAM
TRUTH TABLE FOR TAG AND DATA RAMs (X = Don't Care)
COE H L X CWE H H L Mode Output Disabled Read Write VCC Current ICCA ICCA ICCA Output High-Z Dout High-Z Cycle -- Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Temperature Under Bias Operating Temperature Storage Temperature - Plastic for Tag for Data Symbol VCC5 VCC3 Vin, Vout Iout Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to + 5.0 - 0.5 to VCC + 0.5* 20 - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
* For data RAMs, VCC + 2.0 V ac to VSS - 2.0 V ac (pulse width 20 ns). NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
v
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC3 = 3.3 V 5%, VCC5 = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Tag RAM Data RAM and Latch Symbol VCC VIH VIL Min 4.75 3.135 2.2 - 0.5** Typ 5.0 3.3 -- 0.0 Max 5.25 3.465 VCC + 0.3* 0.8 Unit V V V
* For Tag, VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns). For Data, VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 10% tAVAV (min)). ** For Tag, VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns). For Data, VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 10% tAVAV (min)).
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (COE = VIH, Vout = 0 to VCC) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) CMOS Output Low Voltage (IOL = 100 A) CMOS Output High Voltage (IOH = - 100 A) NOTE: NOTE: Good decoupling of the local power supply should always be used. Symbol Ilkg(I) Ilkg(O) VOL VOH VOL2 VOH2 Min -- -- -- 2.4 -- VCC - 0.1 Max 2 2 0.4 -- 0.1 -- Unit A A V V V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) Symbol ICCA Max 780 Unit mA
MOTOROLA FAST SRAM
MCM64AF32 5
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (TWE, CALE, CWE0 - CWE7) (A5 - A17) (CAA3, CAA4, CAB3, CAB4) (COE) (DQ0 - DQ63) (TIO0 - TIO7) Symbol Cin Max 8 14 26 50 8 10 Unit pF
Input/Output Capacitance
CI/O
pF
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
DATA RAMs READ CYCLE (See Note 1)
-15 Parameter Read Cycle Time Address Access Time (CAAx, CABx) Latched Address Access Time (A5 - A17) Latched Address to CALE Low Setup Time Latched Address to CALE Low Hold Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z Power Up Time Symbol tAVAV tAVQV tLAVQV tAVCALL tCALAX tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH Min 15 -- -- 4 3 -- -- 4 4 0 0 0 0 Max -- 15 22 -- -- 15 8 -- -- 8 -- 7 -- 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 3 Notes 2
Power Down Time tEHICCL -- NOTES: 1. CWE is high for read cycle. 2. All timings are referenced from the last valid address to the first address transition. 3. Addresses valid prior to or coincident with CS going low. 4. At any given voltage and temperature, tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (COE = VIL).
AC TEST LOADS
+ 3.3 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 353 5 pF 319
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MCM64AF32 6
MOTOROLA FAST SRAM
DATA RAMs FIRST ACCESS READ CYCLE (See Note 7)
A5 - A17 tAVCALL CALE tCALAX
DQx
PREVIOUS DATA tLAVQV
DATA VALID
DATA RAMs BURST ACCESS READ CYCLE (CALE VIL) (See Note 7)
tAVAV CAAx, CABx (CACHE ADDRESS A/B) tAVQV DQx PREVIOUS DATA tAXQX DATA VALID
DATA RAMs READ CYCLE 3 (CALE VIL) (See Note 3)
tAVAV CAAx, CABx (CACHE ADDRESS A/B)
COE (OUTPUT ENABLE)
tGLQV tGHQZ
DQX
HIGH-Z
tGLQX DATA VALID tAVQV
HIGH-Z
MOTOROLA FAST SRAM
MCM64AF32 7
DATA RAMs WRITE CYCLE (CWE Controlled, See Notes 1 and 2)
-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Write Pulse Width, COE High Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX Min 15 0 12 12 10 7 0 0 4 Max -- -- -- -- -- -- -- 7 -- Unit ns ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 4 Notes 3
Write Recovery Time tWHAX 0 -- ns NOTES: 1. A write occurs when CWE low. 2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If COE VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested.
DATA RAMs WRITE CYCLE (CALE VIH) (CWE Controlled, See Notes 1 and 2)
A5 - A17 tAVAV CAAx, CABx (CACHE ADDRESS A/B) tAVWH tWLEH tWLWH CWEx (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ HIGH-Z Q (DATA OUT) HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MCM64AF32 8
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 and 5)
- 15 Parameter Read Cycle Time Address Access Time Output Hold from Address Change Symbol tAVAV tAVQV tAXQX Min 15 -- 4 Max -- 15 -- Unit ns ns ns 3, 4 Notes 2
NOTES: 1. CWE is high for read cycle. 2. All timings are referenced from the last valid address to the first address transition. 3. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (COE = VIL).
TAG RAM READ CYCLE (See Note 5)
tAVAV A5 - A17 tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
MOTOROLA FAST SRAM
MCM64AF32 9
TAG RAM WRITE CYCLE (See Notes 1 and 2)
- 15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 7 0 0 4 0 Max -- -- -- -- -- 7 -- -- Unit ns ns ns ns ns ns ns ns 5, 6, 7 5, 6, 7 Notes 3
NOTES: 1. A write occurs when CWE is low. 2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If COE VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE (See Notes 1 and 2)
tAVAV A5 - A17 tAVWH tWLWH TWE (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
64AF32
XX
XX
Speed (15 = 15 ns) Package (SG = Gold Pad SIMM)
Full Part Number -- MCM64AF32SG15
MCM64AF32 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
CARD EDGE MODULE 160-LEAD CASE TBD A E C
NOTE 4
B
-Y- VIEW AA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE E E EE E
FULL R 80 43 42 1 2X
COMPONENT AREA
P
V
NOTE 4
F
AC
-X-
L
M
AB
NOTE 5
J -T- SIDE VIEW
NOTE 6
FRONT VIEW
0.012 (0.3)
M
R
R
W
(N)
EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE EEEEEEEEEEEEEEEE EEEEEEE EEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE EEEEEE EE E E EE
160
EEE E E EEE E E EEE E E EEE E E EEE E E
160X
D 0.004 (0.1)
L
TYX
S
160X
H
160X
K
156X
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.290 1.310 --- 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC --- 0.030 0.055 0.069 0.210 --- 1.955 1.965 2.155 2.165 0.110 REF 0.125 --- 0.285 0.305 0.157 --- 0.040 0.060 --- 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 32.77 33.27 --- 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC --- 0.51 1.40 1.75 5.33 --- 49.66 49.91 54.74 54.99 2.79 REF 3.18 --- 7.24 7.75 3.99 --- 1.02 1.52 --- 6.66 1.83 1.93
VIEW AA
123
122
81
COMPONENT AREA
BACK VIEW
MCM64AF32 11
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM64AF32 12
*MCM64AF32/D*
MOTOROLA MCM64AF32/D FAST SRAM

▲Up To Search▲

Price & Availability of MCM64AF32SG15

	To Download MCM64AF32SG15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .